Light emitting diode packages

ABSTRACT

Solid-state lighting devices including light-emitting diodes (LEDs) and LED packages are disclosed. LED packages are provided with improved thermal and/or electrical coupling between LED chips and submounts or lead frames. Various configurations of submounts with via arrangements are disclosed to provide improved coupling between LED chips and submounts. LED chip contacts are disclosed with one or more openings that are registered with vias to provide more uniform mounting. Multiple LED chips may be arranged around a thermally conductive element on a submount, and a via in the submount may be registered with the thermally conductive element. Subassemblies are provided between LED chips and lead frames to improve electrical and thermal coupling. Underfill materials may be arranged between LED chips and lead frames to provide improved mechanical support.

RELATED APPLICATIONS

This application is a division of U.S. patent application Ser. No.16/249,246, filed Jan. 16, 2019, the disclosure of which is herebyincorporated herein by reference in its entirety.

TECHNICAL FIELD

The present disclosure relates to solid-state lighting devices includinglight-emitting diodes (LEDs) and more particularly to LED packages.

BACKGROUND

Solid-state lighting devices such as light-emitting diodes (LEDs) areincreasingly used in both consumer and commercial applications.Advancements in LED technology have resulted in highly efficient andmechanically robust light sources with a long service life. Accordingly,modern LEDs have enabled a variety of new display applications and arebeing increasingly utilized for general illumination applications, oftenreplacing incandescent and fluorescent light sources.

LEDs are solid-state devices that convert electrical energy to light andgenerally include one or more active layers of semiconductor material(or an active region) arranged between oppositely doped n-type andp-type layers. When a bias is applied across the doped layers, holes andelectrons are injected into the one or more active layers where theyrecombine to generate emissions such as visible light or ultravioletemissions. An LED chip typically includes an active region that may befabricated, for example, from silicon carbide, gallium nitride, galliumphosphide, aluminum nitride, gallium arsenide-based materials, and/orfrom organic semiconductor materials. LED packages are solid-statedevices that incorporate one or more LED chips into a packaged device.An LED chip may be enclosed in a component package to provideenvironmental and/or mechanical protection, light focusing and the like.

Typically, it is desirable to operate LED chips and LED packages at thehighest light emission efficiencies possible, which can be measured bythe emission intensity in relation to the input power (e.g., in lumensper watt). As light emission intensities of LED chips and LED componentscontinue to increase, more heat can be generated from LED chips, whichcan adversely impact operating efficiencies. Additionally, challengesexist in manufacturing LED packages that incorporate LED chips mountedto die attach pads. The art continues to seek improved LEDs andsolid-state lighting devices having increased light output and increasedlight emission efficiencies without impairing manufacturability andreliability of such devices, while providing desirable illuminationcharacteristics capable of overcoming challenges associated withconventional lighting devices.

SUMMARY

The present disclosure relates to solid-state lighting devices includinglight-emitting diodes (LEDs), and more particularly to LED packages. LEDpackages as disclosed herein are configured to provide improved thermaland/or electrical coupling between LED chips and submounts or betweenLED chips and lead frames. In certain embodiments, LED packages includesubmounts incorporating electrically conductive vias, with such viasbeing configured to provide improved thermal contact between LED chipsand submounts. LED chips may further include contacts with one or moreopenings that are registered with vias to provide more uniform mountingbetween LED chips and submounts. In certain embodiments, multiple LEDchips are arranged around a thermally conductive element on a surface ofa submount, and a via in the submount may be registered with thethermally conductive element. In certain embodiments, subassemblies areprovided between LED chips and lead frames to improve electrical andthermal coupling. In certain embodiments, underfill materials arearranged between LED chips and lead frames to provide improvedmechanical support. According to the embodiments disclosed herein, LEDpackages are provided with thermal capabilities that allow operation athigher powers with increased power densities.

In one aspect, an LED package comprises: a submount comprising a firstface, a second face that opposes the first face, a die attach pad on thefirst face, and at least one via that comprises an electricallyconductive material and that extends between the first face and thesecond face, wherein the die attach pad is registered with the at leastone via; and an LED chip comprising a contact pad that is coupled withthe die attach pad, wherein the contact pad defines at least one openingthat is registered with the at least one via. The die attach pad may beelectrically coupled with the at least one via. In certain embodiments,each opening of the at least one opening comprises a recess having amaximum depth smaller than a thickness of the contact pad. In certainembodiments, each opening of the at least one opening comprises anaperture extending through an entire thickness of the contact pad. Incertain embodiments, the at least one via comprises a plurality of vias,wherein the die attach pad is registered with the plurality of vias. Incertain embodiments, the at least one opening comprises a plurality ofopenings that are registered with the plurality of vias. In certainembodiments, the at least one via comprises a plurality of vias thatoverlap with one another to form a trench via. In certain embodiments,the at least one opening comprises a trench opening that is registeredwith the trench via. In certain embodiments, the LED chip is one of aplurality of LED chips that are mounted on the submount; the at leastone via comprises a plurality of vias; the die attach pad is one of aplurality of die attach pads on the first face; and each LED chip of theplurality of LED chips is coupled with a different die attach pad of theplurality of die attach pads, and each LED chip comprises a contact padthat defines an opening registered with a different via of the pluralityof vias. The LED chip may comprise a multiple-junction LED chip that ismounted on the submount. In certain embodiments, the at least one viacomprises three vias that are positioned relative to one another in thesubmount to form vertices of a triangle.

In another aspect, an LED package comprises: a submount comprising afirst face, a second face that opposes the first face, a first dieattach pad on the first face, a second die attach pad on the first face,a first plurality of vias registered with the first die attach pad, anda second plurality of vias registered with the second die attach pad;and an LED chip comprising a primary light emitting face, a mountingface that opposes the primary light emitting face, an anode contact padon the mounting face, and a cathode contact pad on the mounting face;wherein the anode contact pad is coupled with the first die attach pad,and the cathode contact pad is coupled with the second die attach pad.The LED package of claim B1, wherein the first plurality of vias iselectrically coupled with the first die attach pad, and the secondplurality of vias is electrically coupled with the second die attachpad. In certain embodiments, the anode contact pad comprises a pluralityof openings, and openings of the plurality of openings are registeredwith vias of the first plurality of vias. In certain embodiments, thecathode contact pad comprises a plurality of openings, and openings ofthe plurality of openings are registered with vias of the secondplurality of vias. In certain embodiments, the anode contact padcomprises a first plurality of openings, and openings of the firstplurality of openings are registered with vias of the first plurality ofvias; and the cathode contact pad comprises a second plurality ofopenings, and openings of the second plurality of openings areregistered with vias of the second plurality of vias. The submount maycomprise at least one additional via that is arranged outside of amounting area defined by lateral boundaries of the LED chip. In certainembodiments, at least one via of the first plurality of vias extendsinto but not completely through the first die attach pad, and at leastone via of the second plurality of vias extends into but not completelythrough the second die attach pad. The first plurality of vias and thesecond plurality of vias may be electrically isolated from the first dieattach pad and the second die attach pad. In certain embodiments, atleast one via of the first plurality of vias and/or at least one of thesecond plurality of vias extends in the submount at an oblique anglebetween the first face and the second face.

In another aspect, an LED package comprise: a first submount comprisinga first face and a second face that opposes the first face, the firstsubmount further comprising a plurality of vias that extend between thefirst face and the second face; a second submount comprising a first dieattach pad, wherein the first die attach pad is registered with theplurality of vias; and an LED chip comprising a first contact pad thatis coupled with the first die attach pad. In certain embodiments, thesecond submount is arranged between the LED chip and the first submount.In certain embodiments, the plurality of vias extend less than an entiredistance between the first face and the second face of the firstsubmount. In certain embodiments, the plurality of vias extendcompletely through the first submount.

In another aspect, an LED package comprises: a submount comprising afirst face and a second face that opposes the first face, the submountfurther comprising a via that comprises a thermally conductive materialand that extends between the first face and the second face; a thermallyconductive element on the first face and registered with the via; and aplurality of LED chips on the first face, wherein each LED chip of theplurality of LED chips is arranged adjacent to a different lateral edgeof the thermally conductive element. In certain embodiments, the via isconfigured with a same cross-sectional width or diameter as thethermally conductive element. In certain embodiments, the via isconfigured with a larger cross-sectional width or diameter than thethermally conductive element. The LED package may further comprise apackage bond pad on the second face of the submount, wherein the packagebond pad is registered with the via. In certain embodiments, a corner ofeach LED chip of the plurality of LED chips is arranged closest to adifferent corner of the thermally conductive element.

In another aspect, an LED package comprises: an LED chip mounted to alead frame; and a subassembly arranged between the LED chip and the leadframe, wherein the subassembly comprises a metal submount that isthermally coupled between the LED chip and the lead frame. In certainembodiments, the subassembly further comprises: a first die attach padthat is configured to be electrically coupled with a first contact padof the LED chip; and a second die attach pad that is configured to beelectrically coupled with a second contact pad of the LED chip. Incertain embodiments, the first die attach pad and the second die attachpad are electrically coupled to different portions of the lead frame bywirebonds. In certain embodiments, the subassembly further comprises adielectric layer arranged between the first die attach pad and the metalsubmount, and arranged between the second die attach pad and the metalsubmount. In certain embodiments, the LED chip is arranged in aflip-chip configuration on the first die attach pad and the second dieattach pad. The LED package may further comprise an underfill materialarranged between the subassembly and the lead frame.

In another aspect, an LED package comprises: an LED chip mounted to alead frame; a underfill material arranged between the LED chip and thelead frame; and an encapsulant material arranged on the LED chip and theunderfill material. In certain embodiments, a first contact of the LEDchip is electrically and mechanically coupled with a first lead frameportion, and a second contact of the LED chip is electrically andmechanically coupled with a second lead frame portion. In certainembodiments, the underfill material is arranged between the first leadframe portion and the second lead frame portion. In certain embodiments,the underfill material is arranged between the first contact of the LEDchip and the second contact of the LED chip. In certain embodiments, theunderfill material comprises light altering particles. In certainembodiments, the underfill material comprises a material with a higherdurometer value on a Shore D hardness scale than the encapsulantmaterial.

In another aspect, an LED package comprises: a submount comprising afirst face, a second face that opposes the first face, a die attach padon the first face, and a plurality of vias registered with the dieattach pad, wherein outermost vias of the plurality of vias are arrangedto form vertices of a non-rectangular polygonal shape; and an LED chipcomprising a primary light emitting face and a mounting face thatopposes the primary light emitting face, and at least a portion of themounting face is thermally coupled to the die attach pad. In certainembodiments, the plurality of vias are arranged in an asymmetricpattern. In certain embodiments, a spacing between adjacent vias of theplurality of vias is smaller near the center of the die attach pad thanalong a perimeter of the die attach pad. In certain embodiments, theplurality of vias comprises three vias that are positioned relative toone another in the submount to form vertices of a triangle.

In another aspect, an LED package comprises: a submount comprising afirst face, a second face that opposes the first face, a die attach padon the first face, and a plurality of vias registered with the dieattach pad, wherein a spacing between adjacent vias of the plurality ofvias is smaller in certain areas of the die attach pad than in otherareas the die attach pad; and an LED chip comprising a primary lightemitting face and a mounting face that opposes the primary lightemitting face, and at least a portion of the mounting face is thermallycoupled to the die attach pad. In certain embodiments, the spacingbetween the adjacent vias of the plurality of vias is smaller near thecenter of the die attach pad than along a perimeter of the die attachpad. In certain embodiments, the spacing between the adjacent vias ofthe plurality of vias is smaller along a perimeter of the die attachpad. In certain embodiments, the plurality of vias form an array ofclosely spaced via clusters along the die attach pad. In certainembodiments, the die attach pad is electrically coupled with theplurality of vias. In certain embodiments, the die attach pad iselectrically isolated with the plurality of vias.

In another aspect, any one or more aspects or features described hereinmay be combined with any one or more other aspects or features foradditional advantage.

Other aspects and embodiments will be apparent from the detaileddescription and accompanying drawings.

Those skilled in the art will appreciate the scope of the presentdisclosure and realize additional aspects thereof after reading thefollowing detailed description of the preferred embodiments inassociation with the accompanying drawing figures.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a representative LED package thatincludes an LED chip mounted on a submount.

FIG. 2A is a cross-sectional view of an LED package that includes one ormore openings that are registered with vias according to embodimentsdisclosed herein.

FIG. 2B is a top view of a portion of the first face of the submount ofFIG. 2A.

FIG. 2C is a bottom view of the mounting face of the LED chip of FIG.2A.

FIG. 3A is a top view of a portion of the first face of a submount thatis configured for multiple LED chips or a multiple-junction LED chip.

FIG. 3B is a bottom view of the mounting face of a multiple-junction LEDchip that is configured to be mounted on the submount of FIG. 3A.

FIG. 4A is a top view of a portion of the first face of a submount thatincludes vias configured in a triangular arrangement.

FIG. 4B is a bottom view of the mounting face of an LED chip that isconfigured to be mounted on the submount of FIG. 4A.

FIG. 5A is a cross-sectional view of an LED package that includes aplurality of vias arranged between particular die attach pads andpackage bond pads according to embodiments disclosed herein.

FIG. 5B is a top view of a portion of the first face of the submount ofFIG. 5A.

FIG. 5C is a bottom view of the mounting face of the LED chip of FIG.5A.

FIG. 5D is a top view of a portion of the first face of the submount ofFIG. 5A with a different arrangement of vias.

FIG. 5E is a top view of a portion of the first face of the submount ofFIG. 5A with a different arrangement of vias.

FIG. 5F is a top view of a portion of the first face of the submount ofFIG. 5A with a different arrangement of vias.

FIG. 6 is a cross-sectional view of an LED package that includes aplurality of vias arranged in a submount according to embodimentsdisclosed herein.

FIG. 7A is a cross-sectional view of an LED package that includes aplurality of vias, at least some of which are arranged at oblique angleswithin a submount according to embodiments disclosed herein.

FIG. 7B is a cross-sectional view of the LED package of FIG. 7A where atleast some of the plurality of vias are arranged at different obliqueangles according to embodiments disclosed herein.

FIG. 8 is a cross-sectional view of an LED package that includes asecond submount arranged between an LED chip and a plurality of viasaccording to embodiments disclosed herein.

FIG. 9 is a cross-sectional view of an LED package that includes dieattach pads having thicknesses configured to prevent protruding viasfrom extending completely through the die attach pads according toembodiments disclosed herein.

FIG. 10A is a top view of at least a portion of the first face of asubmount that includes one or more trench vias according to embodimentsdisclosed herein.

FIG. 10B is a bottom view of the mounting face of an LED chip that isconfigured to be mounted on the submount of FIG. 10A.

FIG. 11A is a top view of at least a portion of an LED package thatincludes a thermally conductive element arranged between a plurality ofLED chips on a face of a submount according to embodiments disclosedherein.

FIG. 11B is a cross-sectional view of the LED package of FIG. 11A takenalong the section line labeled 11B in FIG. 11A.

FIGS. 11C, 11D, and 11E are top views of at least portions of LEDpackages similar to the LED package of FIG. 11A, but with differentarrangements of LED chips on the submount.

FIG. 12 is a cross-sectional view of an LED package that includes a leadframe according to embodiments disclosed herein.

FIG. 13 is a cross-sectional view of an LED package that includes anunderfill material configured to provide additional mechanical supportbetween an LED chip and a lead frame.

DETAILED DESCRIPTION

The embodiments set forth below represent the necessary information toenable those skilled in the art to practice the embodiments andillustrate the best mode of practicing the embodiments. Upon reading thefollowing description in light of the accompanying drawing figures,those skilled in the art will understand the concepts of the disclosureand will recognize applications of these concepts not particularlyaddressed herein. It should be understood that these concepts andapplications fall within the scope of the disclosure and theaccompanying claims.

It will be understood that, although the terms first, second, etc. maybe used herein to describe various elements, these elements should notbe limited by these terms. These terms are only used to distinguish oneelement from another. For example, a first element could be termed asecond element, and, similarly, a second element could be termed a firstelement, without departing from the scope of the present disclosure. Asused herein, the term “and/or” includes any and all combinations of oneor more of the associated listed items.

It will be understood that when an element such as a layer, region, orsubstrate is referred to as being “on” or extending “onto” anotherelement, it can be directly on or extend directly onto the other elementor intervening elements may also be present. In contrast, when anelement is referred to as being “directly on” or extending “directlyonto” another element, there are no intervening elements present.Likewise, it will be understood that when an element such as a layer,region, or substrate is referred to as being “over” or extending “over”another element, it can be directly over or extend directly over theother element or intervening elements may also be present. In contrast,when an element is referred to as being “directly over” or extending“directly over” another element, there are no intervening elementspresent. It will also be understood that when an element is referred toas being “connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, there are nointervening elements present.

Relative terms such as “below” or “above” or “upper” or “lower” or“horizontal” or “vertical” may be used herein to describe a relationshipof one element, layer, or region to another element, layer, or region asillustrated in the Figures. It will be understood that these terms andthose discussed above are intended to encompass different orientationsof the device in addition to the orientation depicted in the Figures.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the disclosure.As used herein, the singular forms “a,” “an,” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises,”“comprising,” “includes,” and/or “including” when used herein specifythe presence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this disclosure belongs. It willbe further understood that terms used herein should be interpreted ashaving a meaning that is consistent with their meaning in the context ofthis specification and the relevant art and will not be interpreted inan idealized or overly formal sense unless expressly so defined herein.

The present disclosure relates to solid-state lighting devices includinglight-emitting diodes (LEDs) and more particularly to LED packages. LEDpackages as disclosed herein are configured to provide improved thermaland/or electrical coupling between LED chips and submounts or betweenLED chips and lead frames. In certain embodiments, LED packages includesubmounts with via arrangements configured to provide improved thermalcontact between LED chips and submounts. LED chips may further includecontacts with one or more openings that are registered with vias toprovide more uniform mounting between LED chips and submounts. Incertain embodiments, multiple LED chips are arranged around a thermallyconductive element on a surface of a submount, and a via in the submountmay be registered with the thermally conductive element. In certainembodiments, subassemblies are provided between LED chips and leadframes to improve electrical and thermal coupling. In certainembodiments, underfill materials are arranged between LED chips and leadframes to provide improved mechanical support. According to theembodiments disclosed herein, LED packages are provided with thermalcapabilities that allow operation at higher powers with increased powerdensities.

An LED chip typically comprises an active LED structure or region thatcan have many different semiconductor layers arranged in different ways.The fabrication and operation of LEDs and their active structures aregenerally known in the art and are only briefly discussed herein. Thelayers of the active LED structure can be fabricated using knownprocesses with a suitable process being fabrication using metal organicchemical vapor deposition. The layers of the active LED structure cancomprise many different layers and generally comprise an active layersandwiched between n-type and p-type oppositely doped epitaxial layers,all of which are formed successively on a growth substrate. It isunderstood that additional layers and elements can also be included inthe active LED structure, including, but not limited to, buffer layers,nucleation layers, super lattice structures, un-doped layers, claddinglayers, contact layers, and current-spreading layers and lightextraction layers and elements. The active layer can comprise a singlequantum well, a multiple quantum well, a double heterostructure, orsuper lattice structures.

The active LED structure can be fabricated from different materialsystems, with some material systems being Group III nitride-basedmaterial systems. Group III nitrides refer to those semiconductorcompounds formed between nitrogen (N) and the elements in Group III ofthe periodic table, usually aluminum (Al), gallium (Ga), and indium(In). Gallium nitride (GaN) is a common binary compound. Group IIInitrides also refer to ternary and quaternary compounds such as aluminumgallium nitride (AlGaN), indium gallium nitride (InGaN), and aluminumindium gallium nitride (AlInGaN). For Group III nitrides, silicon (Si)is a common n-type dopant and magnesium (Mg) is a common p-type dopant.Accordingly, the active layer, n-type layer, and p-type layer mayinclude one or more layers of GaN, AlGaN, InGaN, and AlInGaN that areeither undoped or doped with Si or Mg for a material system based onGroup III nitrides. Other material systems include silicon carbide(SiC), organic semiconductor materials, and other Group III-V systemssuch as gallium phosphide (GaP), gallium arsenide (GaAs), and relatedcompounds.

The active LED structure may be grown on a growth substrate that caninclude many materials, such as sapphire, SiC, aluminum nitride (AlN),GaN, with a suitable substrate being a 4H polytype of SiC, althoughother SiC polytypes can also be used including 3C, 6H, and 15Rpolytypes. SiC has certain advantages, such as a closer crystal latticematch to Group III nitrides than other substrates and results in GroupIII nitride films of high quality. SiC also has a very high thermalconductivity so that the total output power of Group III nitride deviceson SiC is not limited by the thermal dissipation of the substrate.Sapphire is another common substrate for Group III nitrides and also hascertain advantages, including being lower cost, having establishedmanufacturing processes, and having good light transmissive opticalproperties.

Different embodiments of the active LED structure can emit differentwavelengths of light depending on the composition of the active layerand n-type and p-type layers. In some embodiments, the active LEDstructure emits blue light with a peak wavelength range of approximately430 nanometers (nm) to 480 nm. In other embodiments, the active LEDstructure emits green light with a peak wavelength range of 500 nm to570 nm. In other embodiments, the active LED structure emits red lightwith a peak wavelength range of 600 nm to 650 nm.

The LED chip can also be covered with one or more lumiphoric or otherconversion materials, such as phosphors, such that at least some of thelight from the LED chip is absorbed by the one or more phosphors and isconverted to one or more different wavelength spectra according to thecharacteristic emission from the one or more phosphors. In someembodiments, the combination of the LED chip and the one or morephosphors emits a generally white combination of light. The one or morephosphors may include yellow (e.g., YAG:Ce), green (e.g., LuAg:Ce), andred (e.g., Ca_(i-x-y)Sr_(x)Eu_(y)AlSiN₃) emitting phosphors, andcombinations thereof. Lumiphoric materials as described herein may be orinclude one or more of a phosphor, a scintillator, a lumiphoric ink, aquantum dot material, a day glow tape, and the like. Lumiphoricmaterials may be provided by any suitable means, for example, directcoating on one or more surfaces of an LED, dispersal in an encapsulantmaterial configured to cover one or more LEDs, and/or coating on one ormore optical or support elements (e.g., by powder coating, inkjetprinting, or the like). In certain embodiments, lumiphoric materials maybe downconverting or upconverting, and combinations of bothdownconverting and upconverting materials may be provided. In certainembodiments, multiple different (e.g., compositionally different)lumiphoric materials arranged to produce different peak wavelengths maybe arranged to receive emissions from one or more LED chips. In someembodiments, one or more phosphors may include yellow phosphor (e.g.,YAG:Ce), green phosphor (e.g., LuAg:Ce), and red phosphor (e.g.,Ca_(i-x-y)Sr_(x)Eu_(y)AlSiN₃) and combinations thereof. One or morelumiphoric materials may be provided on one or more portions of an LEDchip and/or a submount in various configurations. In certainembodiments, one or more surfaces of LED chips may be conformally coatedwith one or more lumiphoric materials, while other surfaces of such LEDchips and/or associated submounts may be devoid of lumiphoric material.In certain embodiments, a top surface of an LED chip may includelumiphoric material, while one or more side surfaces of an LED chip maybe devoid of lumiphoric material. In certain embodiments, all orsubstantially all outer surfaces of an LED chip (e.g., other thancontact-defining or mounting surfaces) are coated or otherwise coveredwith one or more lumiphoric materials. In certain embodiments, one ormore lumiphoric materials may be arranged on or over one or moresurfaces of an LED chip in a substantially uniform manner. In otherembodiments, one or more lumiphoric materials may be arranged on or overone or more surfaces of an LED chip in a manner that is non-uniform withrespect to one or more of material composition, concentration, andthickness. In certain embodiments, the loading percentage of one or morelumiphoric materials may be varied on or among one or more outersurfaces of an LED chip. In certain embodiments, one or more lumiphoricmaterials may be patterned on portions of one or more surfaces of an LEDchip to include one or more stripes, dots, curves, or polygonal shapes.In certain embodiments, multiple lumiphoric materials may be arranged indifferent discrete regions or discrete layers on or over an LED chip.

Light emitted by the active layer or region of an LED chip is typicallyomnidirectional in character. For directional applications, internalmirrors or external reflective surfaces may be employed to redirect asmuch light as possible toward a desired emission direction. Internalmirrors may include single or multiple layers. Some multi-layer mirrorsinclude a metal reflector layer and a dielectric reflector layer,wherein the dielectric reflector layer is arranged between the metalreflector layer and a plurality of semiconductor layers. A passivationlayer is arranged between the metal reflector layer and first and secondelectrical contacts, wherein the first electrical contact is arranged inconductive electrical communication with a first semiconductor layer,and the second electrical contact is arranged in conductive electricalcommunication with a second semiconductor layer. For single ormulti-layer mirrors including surfaces exhibiting less than 100%reflectivity, some light may be absorbed by the mirror. Additionally,light that is redirected through the active LED structure may beabsorbed by other layers or elements within the LED chip.

As used herein, a layer or region of an LED is considered to be“reflective” or embody a “mirror” or a “reflector” when at least 80% ofthe emitted radiation that impinges on the layer or region is reflected.In some embodiments, the emitted radiation comprises visible light suchas blue and/or green LEDs with or without lumiphoric materials. In otherembodiments, the emitted radiation may comprise nonvisible light. Forexample, in the context of GaN-based blue and/or green LEDs, silver (Ag)may be considered a reflective material (e.g., at least 80% reflective).In the case of ultraviolet (UV) LEDs, appropriate materials may beselected to provide a desired, and in some embodiments high,reflectivity and/or a desired, and in some embodiments low, absorption.

The present disclosure can be useful for LED chips having a variety ofgeometries, such as vertical geometry or lateral geometry. A verticalgeometry LED chip typically includes anode and cathode connections onopposing sides or faces of the LED chip. A lateral geometry LED chiptypically includes both anode and cathode connections on the same sideof the LED chip that is opposite a substrate, such as a growthsubstrate. In some embodiments, a lateral geometry LED chip may bemounted on a submount of an LED package such that the anode and cathodeconnections are on a face of the LED chip that is opposite the submount.In this configuration, wirebonds may be used to provide electricalconnections with the anode and cathode connections. In otherembodiments, a lateral geometry LED chip may be flip-chip mounted on asurface of a submount of an LED package such that the anode and cathodeconnections are on a face of the active LED structure that is adjacentto the submount. In this configuration, electrical traces or patternsmay be provided on the submount for providing electrical connections tothe anode and cathode connections of the LED chip. In a flip-chipconfiguration, the active LED structure is configured between thesubstrate of the LED chip and the submount for the LED package.Accordingly, light emitted from the active LED structure may passthrough the substrate in a desired emission direction. In someembodiments, the flip-chip LED chip may be configured as described incommonly-assigned U.S. Publication No. 2017/0098746, which is herebyincorporated by reference herein. In some embodiments, an LED packagemay be configured as set forth in the following commonly-assigned U.S.patents and U.S. publications, which are hereby incorporated byreference herein: U.S. Pat. Nos. 8,866,169; 9,070,850; 9,887,327; andU.S. Publication No. 2015/0179903.

FIG. 1 is a cross-sectional view of a representative LED package 10 thatincludes an LED chip 12. The LED chip 12 includes a primary lightemitting face 14 that is opposite a mounting face 16. The LED chip 12 ismounted to a submount 18 such that the mounting face 16 is arrangedbetween the primary light emitting face 14 and the submount 18. Thesubmount 18 can be formed of many different materials, with a preferredmaterial being electrically insulating. Suitable materials include, butare not limited to, ceramic materials such as aluminum oxide or alumina,AlN, or organic insulators like polyimide (PI) and polyphthalamide(PPA). In other embodiments the submount 18 can comprise a printedcircuit board (PCB), sapphire, Si, or any other suitable material. ForPCB embodiments, different PCB types can be used such as standard FR-4PCBs, metal core PCBs, or any other type of PCB. LED packages accordingto the present disclosure can be fabricated using a method that utilizesa submount panel sized to accommodate a plurality of submounts. MultipleLED packages can be formed on the panel, with individual packages beingsingulated from the panel. The LED chip 12 can be mounted to thesubmount 18 using known methods and material mounting such as usingconventional solder materials that may or may not contain a fluxmaterial or dispensed polymeric materials that may be thermally andelectrically conductive, as well as other methods and material mountingsuch as solderless, direct attach, or other conventional attachmentmeans.

The LED package 10 further includes an encapsulant 20 that may provideboth environmental and/or mechanical protection for the LED chip 12. Theencapsulant 20 may also be referred to as an encapsulant layer. Manydifferent materials can be used for the encapsulant 20, includingsilicones, plastics, epoxies or glass, with a suitable material beingcompatible with molding processes. Silicone is suitable for molding andprovides suitable optical transmission properties for light emitted fromthe LED chip 12. In some embodiments, the encapsulant 20 can be moldedinto the shape of a lens 20′. Different molding techniques may providethe lens 20′ with many different shapes depending on the desiredemission pattern for the LED package 10. One suitable shape as shown inFIG. 1 is hemispheric, with some examples of alternative shapes beingellipsoid bullet, flat, hex-shaped and square. In certain embodiments, asuitable shape includes both curved and planar surfaces, such as ahemispheric top portion with planar side surfaces. It is understood thatthe encapsulant 20 can also be textured to improve light extraction. Insome embodiments, a portion of the encapsulant 20 may form a protectivelayer that covers any portion of the submount 18 that is not covered bythe shape of the lens 20′. For example, in FIG. 1, where thehemispherical shape of the lens 20′ ends, a planar extension ofencapsulant 20 material may be provided from the lens 20′ to one or moreperimeter edges of the submount 18 to provide additional protection toelements on the top surface to reduce damage and contamination duringsubsequent processing steps and use. In certain embodiments, theencapsulant 20 may include one or more lumiphoric materials orscattering particles. In other embodiments, one or more lumiphoricmaterials may be provided in a separate layer or layers between the LEDchip 12 and the encapsulant 20.

As illustrated in FIG. 1, the LED chip 12 is arranged on the submount 18in a flip-chip configuration in certain embodiments. In this regard, theLED chip 12 includes a first contact pad 22 and a second contact pad 24on the mounting face 16 that are configured to be mounted andelectrically and thermally coupled to a first die attach pad 26 and asecond die attach pad 28, respectively, that are arranged on thesubmount 18. In certain embodiments, the first contact pad 22 and thesecond contact pad 24 comprise a thickness of in a range of about 1micron (μm) to about 8 μm, or in range of about 3 μm to about 5 μm. Thefirst contact pad 22 and the second contact pad 24 may comprisedifferent ones of an anode contact pad and a cathode contact pad for theLED chip 12. In certain embodiments, the first die attach pad 26 and thesecond die attach pad 28 comprise a thickness in a range of about 1 μmto about 100 μm, or in a range of about 5 μm to about 90 μm, or in arange of about 40 μm to about 80 μm. The first die attach pad 26 and thesecond die attach pad 28 are arranged on a first face 30 of the submount18 that also may support the encapsulant 20. The submount 18 includes asecond face 32 that generally opposes the first face 30. In certainembodiments, the second face 32 of the submount 18 includes a firstpackage bond pad 34 and a second package bond pad 36 that are configuredto receive an external electrical connection for the LED package 10. Forexample, the LED package 10 may be mounted on another board thatincludes electrical traces or leads that correspond with the packagebond pads 34, 36.

In order to electrically couple the package bond pads 34, 36 with theLED chip 12, the submount 18 comprises one or more vias 38 ofelectrically conductive material that extend between the first face 30and the second face 32 of the submount 18. In particular, the vias 38may be configured to be electrically and thermally coupled with the dieattach pads 26, 28 and the package bond pads 34, 36. In certainembodiments, the vias 38 extend completely through the submount 18 toprovide electrical connections between the package bond pads 34, 36 andthe die attach pads 26, 28. In typical manufacturing processes, the vias38 may be formed by punching, cutting, drilling, laser cutting, or laserdrilling of holes in the submount 18, followed by plating or filling theholes with a conductive material such as copper or aluminum, amongothers. In certain embodiments, the vias 38 may comprise across-sectional diameter in a range of about 20 μm to about 200 μm, orin a range of about 50 μm to about 160 μm, or in a range of about 80 μmto about 120 μm. Due to various manufacturing tolerances, the conductivematerial may include gaps or voids that can trap gas within the vias 38.During subsequent assembly steps for the LED package 10, the vias 38 canbe exposed to increased temperatures, such as those experienced duringbonding or curing steps. Increased temperatures can cause some vias 38,particularly those with the gaps or voids, to expand and push up orprotrude from the submount 18, thereby forming what may be referred toas blistered vias. As illustrated in FIG. 1, each via 38 includes atleast a via portion 38′ that protrudes out of the first face 30 andthrough the die attach pads 26, 28. These protruding via portions 38′can provide uneven surfaces for the LED chip 12 to be mounted on. Inthis regard, the protruding via portions 38′ may prevent the contactpads 22, 24 of the LED chip 12 from making good bonds with the dieattach pads 26, 28 of the submount 18, thereby providing poor thermaland electrical coupling between the LED chip 12 and the submount 18.Additionally, gaps between the contact pads 22, 24 and the die attachpads 26, 28 may allow material of the encapsulant 20, e.g. silicone, toform between the contact pads 22, 24 and the die attach pads 26, 28. Thematerial of the encapsulant 20 may expand during subsequent thermalcycling and can lead to the LED chip 12 separating or popping off of thesubmount 18.

According to embodiments disclosed herein, an LED package may includeone or more features configured to provide improved thermal and/orelectrical coupling between LED chips and submounts. In certainembodiments, LED packages may be configured with one or more openings(e.g., recesses or apertures) that are registered with vias in submountsin a manner that allows the vias to expand without degrading thermal orelectrical coupling. Accordingly, LED packages are provided with thermalcapabilities that allow operation at higher powers with increased powerdensities. In certain embodiments, an LED package includes a submountcomprising a first face and a second face that opposes the first face.The submount may further comprise a via that extends between the firstface and the second face, and a die attach pad that is on the first faceand registered with the via. An LED chip may comprise a contact pad thatis coupled with the die attach pad, and the contact pad comprises anopening that is registered with the via. In this manner, the via mayexpand into the opening without degrading thermal or electrical couplingbetween the contact pad of the LED chip and the die attach pad of thesubmount.

FIG. 2A is a cross-sectional view of an LED package 40 that includes oneor more openings 42 that are registered with vias 38 according toembodiments disclosed herein. The LED package 40 includes the LED chip12 with the contact pads 22, 24 coupled with the die attach pads 26, 28of the submount 18 as previously described. The LED package 40 mayfurther include the encapsulant 20, the one or more vias 38 that extendbetween the first face 30 and the second face 32 of the submount 18, andthe package bond pads 34, 36 as previously described. As illustrated inFIG. 2A, the contact pads 22, 24 include the openings 42 that areregistered with the vias 38. In this manner, when the LED chip 12 ismounted to the submount 18, the vias 38 have room to expand within theopenings 42 without compromising thermal or electrical coupling betweenthe contact pads 22, 24 and the die attach pads 26, 28. The openings 42may be formed in the contact pads 22, 24 by selectively removingportions of the contact pads 22, 24 after they have been formed.Alternatively, the openings 42 may be formed concurrently with thecontact pads 22, 24 by way of selective deposition, such as depositionthrough a patterned mask. In certain embodiments, the openings 42 embodyrecesses that extend through less than an entire thickness of thecontact pads 22, 24, with each opening having a maximum depth smallerthan a thickness of the corresponding contact pad 22, 24. In otherembodiments, the openings 42 may embody apertures that extend through anentire thickness of the contact pads 22, 24. The openings 42 may beconfigured to have a same size or a larger size than a maximum width ordiameter of the vias 38. In certain embodiments, the openings 42 maycomprise a similar cross-sectional shape as the vias 38, such ascircles, ovals, squares, or rectangles, among others. In otherembodiments, the openings 42 may comprise cross-sectional shapes thatare different than the vias 38, such as larger square or rectangularshaped openings 42 that are registered with circular vias 38.

FIG. 2B is a top view of a portion of the first face 30 of the submount18 of FIG. 2A. As illustrated, the submount 18 includes the first dieattach pad 26 that is registered with one of the vias 38 and a seconddie attach pad 28 that is registered with a different one of the vias38. FIG. 2C is a bottom view of the mounting face 16 of the LED chip 12of FIG. 2A. The first die attach pad 26 and the second die attach pad 28collectively form a die attach area for the LED chip 12. In particular,the first contact pad 22 of the LED chip 12 is configured for mountingwith the first die attach pad 26 of the submount 18, and the secondcontact pad 24 of the LED chip 12 is configured for mounting with thesecond die attach pad 28 of the submount 18. The contact pads 22, 24include the openings 42 as previously described. The openings 42 areconfigured to be registered or aligned with the vias 38 of the submount18 when the LED chip 12 is mounted on the submount 18. In certainembodiments, the LED chip 12 may include different numbers of contactpads. For example, the LED chip 12 may include a single contact pad thatis registered with a single die attach pad on the submount 18.

According to embodiments disclosed herein, an LED package may includemultiple LED chips or a multiple-junction LED chip mounted to a commonsubmount. The multiple LED chips or the multiple-junction LED chip mayinclude contact pads with openings that are registered with vias in thesubmount. In particular, each LED chip or each LED junction of amultiple-junction LED chip may include a separate contact pad thatcomprises an opening that is registered with a different via of thesubmount.

FIG. 3A is a top view of a portion of the first face 30 of a submount 46that is configured for multiple LED chips or a multiple-junction LEDchip. As illustrated, the submount 46 includes a plurality of first dieattach pads 26-1 to 26-4 and a plurality of second die attach pads 28-1to 28-4. At least one via of the plurality of vias 38 may be registeredwith each of the first die attach pads 26-1 to 26-4 and each of thesecond die attach pads 28-1 to 28-4. Individual pairs of the first andsecond die attach pads 26-1 to 26-4, 28-1 to 28-4 (e.g., a first pairformed by the first die attach pad 26-1 and the second die attach pad28-1) collectively form separate die attach areas for multiple LED chipsor a multiple-junction LED chip. FIG. 3B is a bottom view of themounting face 16 of a multiple-junction LED chip 50 that is configuredto be mounted on the submount 46 of FIG. 3A. The mounting face 16includes a plurality of first contact pads 22-1 to 22-4 and a pluralityof second contact pads 24-1 to 24-4. Each pair of first and secondcontact pads 22-1 to 22-4, 24-1 to 24-4 (e.g., a first pair formed bythe first contact pad 22-1 and the second contact pad 24-1) is arrangedto be electrically coupled with a different junction of themultiple-junction LED chip 50. Different junctions may be formed byisolating separate active layers or active layer regions of themultiple-junction LED chip 50. The openings 42 are configured aspreviously described to be registered or aligned with the vias 38 of thesubmount 46. In other embodiments, multiple LED chips can beindividually mounted on the submount 46 of FIG. 3A. Multiple LED chipsmay have similar structures as described for the multiple-junction LEDchip 50, but with separate LED chips formed along the dashed lines ofFIG. 3B. In certain embodiments, each LED chip of a plurality of LEDchips comprises a separate contact pad with an opening 42 that isregistered with a different via 38 of the submount 46.

According to embodiments disclosed herein, an LED package may include asubmount with multiple vias configured in arrangements that allowimproved mounting surfaces for LED chips. In certain embodiments, asubmount for an LED package comprises vias configured in a triangulararrangement. In particular, a submount may include three vias in atriangular arrangement. As previously described, vias can sometimesexpand and protrude from a surface of a submount, thereby creatinguneven mounting surfaces for LED chips. By having three vias in atriangular arrangement, the vias will form an arbitrary plane such thatthe LED chip may be evenly supported by the three vias, regardless ofany protruding height differences between the vias.

FIG. 4A is a top view of a portion of the first face 30 of a submount 54that includes a plurality of vias 38-1 to 38-3 arranged in the submount54 as previously described and configured in a triangular arrangement(as indicated by the dashed lines in FIG. 4A). In FIG. 4A, one via 38-1is registered with the first die attach pad 26, and the other vias 38-2,38-3 are registered with the second die attach pad 28. In otherembodiments, the order may be reversed such that two vias 38-2, 38-3 areregistered with the first die attach pad 26 and the one via 38-1 isregistered with the second die attach pad 28. In still otherembodiments, the submount 54 may include a single die attach pad forreceiving an LED chip and the single die attach pad may be registeredwith the plurality of vias 38-1 to 38-3. As illustrated in FIG. 4A,three vias 38-1 to 38-3 are positioned relative to one another in thesubmount 54 to form vertices of a triangle. FIG. 4B is a bottom view ofthe mounting face 16 of an LED chip 58 that is configured to be mountedon the submount 54 of FIG. 4A. As illustrated, the first contact pad 22and the second contact pad 24 do not have the openings 42 as previouslydescribed. In this manner, the first contact pad 22 and the secondcontact pad 24 form a generally planar surface that is configured to bemounted on the submount 54 of FIG. 4A. If any of the vias 38-1 to 38-3protrude to different heights above the submount 54, the generallyplanar surface formed by the first contact pad 22 and the second contactpad 24 will self-level across the triangular plane formed by the heightsof the three vias 38-1 to 38-3. In certain embodiments, the firstcontact pad 22 and the second contact pad 24 may further compriseopenings that are registered with the vias 38-1 to 38-3 as previouslydescribed.

According to certain embodiments disclosed herein, an LED package mayinclude a plurality of vias in a submount that are registered between aparticular die attach pad and a particular package bond pad. In certainembodiments, the plurality of vias are electrically and thermallycoupled between the particular die attach pad and the particular packagebond pad to form a plurality of electrically and thermally conductivepaths. Additionally, the plurality of vias may be arranged in closeproximity to one another and, accordingly, the vias will experiencesimilar manufacturing conditions. In this manner, if the plurality ofvias protrude out of the submount as previously described, the vias mayprotrude with similar heights, thereby reducing unevenness with an LEDchip after mounting.

FIG. 5A is a cross-sectional view of an LED package 60 that includes aplurality of vias 38 arranged between particular die attach pads andpackage bond pads according to embodiments disclosed herein. The LEDpackage 60 includes the LED chip 12 with the contact pads 22, 24 mountedon the submount 18 with the die attach pads 26, 28 and the package bondpads 34, 36 as previously described. The encapsulant (20 of FIG. 2A) mayalso be provided on the LED chip 12 and the submount 18 as previouslydescribed. The submount 18 further includes the plurality of vias 38that extend between the first face 30 and the second face 32 of thesubmount 18. Notably, an increased amount of vias 38 are providedbetween the second die attach pad 28 and the second package bond pad 36.In this regard, the vias 38 between the second contact pad 24 and thesecond package bond pad 36 may be in close proximity to one another andmay experience similar manufacturing conditions. Accordingly, if any ofthe vias 38 expand or protrude from the first face 30, the likelihood isthat all of the vias 38 may expand or protrude in a similar manner,thereby providing a more uniform support and contact for the LED chip12. Additionally, the increased amount of vias 38 also providesadditional thermal and electrical paths for the LED chip 12, therebyallowing the LED chip 12 to be operated with higher powers and increasedpower densities. In certain embodiments, an increased amount of vias 38may also be arranged between the first contact pad 22 and the first dieattach pad 26. FIG. 5B is a top view of a portion of the first face 30of the submount 18 of FIG. 5A. As illustrated, a first plurality of vias38 a are registered with the first die attach pad 26 and a secondplurality of vias 38 b are registered with the second die attach pad 28.In certain embodiments, the second plurality of vias 38 b are arrangedwith a shape that is the same or similar to the second die attach pad28. For example, in FIG. 5B, the second die attach pad 28 is configuredas a rectangular polygonal shape and outermost vias 38 b of the secondplurality of vias 38 b are arranged to form vertices of a rectangularpolygonal shape. In this regard, uniform support for the LED chip (12 ofFIG. 5A) may be provided across the second die attach pad 28. FIG. 5C isa bottom view of the mounting face 16 of the LED chip 12 of FIG. 5A. Aswith previous embodiments, the first contact pad 22 of the LED chip 12is configured for mounting with the first die attach pad 26 of thesubmount 18, and the second contact pad 24 of the LED chip 12 isconfigured for mounting with the second die attach pad 28 of thesubmount 18. In certain embodiments, the first contact pad 22 and thesecond contact pad 24 form a generally planar surface that can be evenlymounted over the submount 18. In other embodiments, the contact pads 22,24 may include a first plurality of openings 42 a and a second pluralityof openings 42 b, respectively, as previously described and indicated bydashed lines in FIG. 5C. In certain embodiments, the openings 42 a, 42 bare configured to be registered or aligned respectively with the vias 38a, 38 b of the submount 18 when the LED chip 12 is mounted on thesubmount 18.

FIGS. 5D and 5E are various top views of a portion of the first face 30of the submount 18 of FIG. 5A with different arrangements of the secondplurality of vias 38 b that are registered with the second die attachpad 28. As illustrated, the first plurality of vias 38 a are registeredwith the first die attach pad 26 as previously described. In certainembodiments, outermost vias 38 b of the second plurality of vias 38 bare arranged to form vertices of a non-rectangular polygonal shape. InFIG. 5D, outermost vias 38 b of the second plurality of vias 38 b arearranged to form vertices of a trapezoidal shape. In FIG. 5E, outermostvias 38 b of the second plurality of vias 38 b are arranged to formvertices of a parallelogram. While trapezoid and parallelogram shapesare illustrated in FIGS. 5D and 5E, outermost vias 38 b of the secondplurality of vias 38 b may form other non-rectangular shapes. In thisregard, the second plurality of vias 38 b may be arranged withnon-rectangular polygonal shapes to provide various mounting planes forthe LED chip (12 of FIG. 5A). In certain embodiments, the outermost vias38 b of the second plurality of vias 38 b comprise three vias that arepositioned relative to one another in the submount 18 to form verticesof a triangle. In certain embodiments, the second plurality of vias 38 bmay be arranged in an asymmetric pattern. As previously described, thesecond plurality of vias 38 b may be configured to provide electricalcoupling and/or thermal coupling between the second die attach pad 28and the second package bond pad (36 of FIG. 5A). As shown in FIG. 5F,spacing between adjacent vias 38 b of the second plurality of vias 38 bis smaller near the center of the second die attach pad 28 than along aperimeter of the die attach pad 28. The smaller spacing of the adjacentvias 38 b of the second plurality of vias 38 b may provide localizedareas with increased thermal dissipation capabilities. In FIG. 5F, thesmaller spacing is provided near the center of the second die attach pad28, where heat may tend to concentrate in higher amounts duringoperation. Depending on the particular application and heat profile of aparticular LED package, smaller spacing between adjacent vias 38 b ofthe second plurality of vias 38 b may be arranged in other locations,such as along the perimeter of the second die attach pad 28, or an arrayof closely spaced via clusters arranged across the second die attach pad28.

According to certain embodiments disclosed herein, an LED package mayinclude a submount with vias configured in arrangements that provideimproved thermal dissipation for LED chips. In certain embodiments, atleast some of the vias may be electrically isolated from LED chipsmounted on the submount. In this regard, electrical connections may beprovided to the LED chips by other arrangements, such as wire bonds orother die attach pads that have electrically coupled vias. Theelectrically isolated vias may be provided in the submount in areas thatexperience high amounts of heat during operation, such as below an LEDchip mounted thereon. The vias may be arranged to extend less than anentire distance through the submount. The vias may be arrangedperpendicular to a first face of the submount, or the vias may bearranged at oblique angles within the submount to dissipate heat in morelateral directions. In certain embodiments, a second submount may bearranged between an LED chip and a first submount that includes aplurality of vias.

FIG. 6 is a cross-sectional view of an LED package 62 that includes aplurality of vias 38 a, 38 b arranged in the submount 18 according toembodiments disclosed herein. The LED package 62 includes the LED chip12 with the contact pads 22, 24 mounted on the submount 18 with the dieattach pads 26, 28 and the package bond pads 34, 36 as previouslydescribed. The encapsulant (20 of FIG. 2A) may also be provided on theLED chip 12 and the submount 18 as previously described. The submount 18further includes a first plurality of vias 38 a that are registered withthe first die attach pad 26 and a second plurality of vias 38 b that areregistered with the second die attach pad 28. Notably, the vias 38 a, 38b are configured to extend less than an entire distance between thefirst face 30 and the second face 32 of the submount 18. In certainembodiments, the first plurality of vias 38 a and the second pluralityof vias 38 b are electrically isolated from the first die attach pad 26and the second die attach pad 28. In this manner, while not electricallycoupled to the LED chip 12, the vias 38 a, 38 b are configured todissipate heat that radiates into the submount 18 away from the LED chip12. In particular, the vias 38 a, 38 b may be configured to dissipateheat through the submount 18 and to a thermal pad 61. The thermal pad 61may be arranged on the second face 32 of the submount 18. The thermalpad 61 may comprise one or more metal layers, similar to the packagebond pads 34, 36. In certain embodiments, the package bond pads 34, 36are electrically coupled with the die attach pads 26, 28 by way ofelectrically conductive vias or paths 63 a, 63 b through the submount18. The die attach pads 26, 28 may be configured to extend on the firstface 30 to lateral edges of the submount 18 to provide increased surfacearea for thermal dissipation on the first face 30. As illustrated, thevias 38 a, 38 b are configured in a direction perpendicular to the firstface 30 of the submount 18. Accordingly, heat may be dissipated througha shorter path through the submount 18, where in turn, the heat may bedissipated laterally through the thermal pad 61 or into another materialon which the LED package 62 may be mounted, such as a fixture housing, aheat sink, or the like.

FIG. 7A is a cross-sectional view of an LED package 64 that includes aplurality of vias 38, at least some of which are arranged at obliqueangles within the submount 18 according to embodiments disclosed herein.The LED package 64 includes the LED chip 12 with the contact pads 22, 24mounted on the submount 18 with the die attach pads 26, 28, the packagebond pads 34, 36, and the electrically conductive vias or paths 63 a, 63b as previously described. The encapsulant (20 of FIG. 2A) may also beprovided on the LED chip 12 and the submount 18 as previously described.Notably, at least one of the plurality of vias 38 extends in thesubmount 18 at an oblique angle from the first face 30 to the secondface 32. In this manner heat may be dissipated away from the LED chip 12in multiple directions through the submount 18, including along thermalpaths with oblique angles where heat dissipates laterally away from theLED chip 12 as it dissipates through the submount 18. The plurality ofvias 38 may be thermally coupled with the thermal pad 61 as previouslydescribed. In this regard, heat that may be concentrated directly underthe LED chip 12 may be distributed to the thermal pad 61 with increasedlateral spreading.

FIG. 7B is a cross-sectional view of the LED package 64 of FIG. 7A whereat least some of the plurality of vias 38 are arranged at differentoblique angles within the submount 18 according to embodiments disclosedherein. The LED package 64 includes the LED chip 12 with the contactpads 22, 24 mounted on the submount 18 with the die attach pads 26, 28,the package bond pads 34, 36, and the electrically conductive vias orpaths 63 a, 63 b as previously described. The encapsulant (20 of FIG.2A) may also be provided on the LED chip 12 and the submount 18 aspreviously described. Notably, at least one of the plurality of vias 38extends in the submount 18 at an oblique angle from the first face 30 tothe second face 32. In this manner heat may be dissipated in multipledirections through the submount 18, including along thermal paths atoblique angles where heat dissipates laterally toward the thermal pad 61as it dissipates through the submount 18. In this regard, heat that mayspread laterally along the first face 30 may be directed through thesubmount 18 and to the thermal pad 61.

FIG. 8 is a cross-sectional view of an LED package 66 that includes asecond submount 68 arranged between the LED chip 12 and the plurality ofvias 38 a, 38 b according to embodiments disclosed herein. The LEDpackage 66 includes the LED chip 12 with the contact pads 22, 24 and thesubmount 18, also referred to as a first submount 18, with the packagebond pads 34, 36 as previously described. The encapsulant (20 of FIG.2A) may also be provided on the LED chip 12 and the second submount 68as previously described. The second submount 68 is arranged between theLED chip 12 and the first submount 18, and the second submount 68accordingly includes the die attach pads 26, 28 as previously described.The first submount 18 includes the first plurality of vias 38 a that areregistered with the first die attach pad 26 and the second plurality ofvias 38 b that are registered with the second die attach pad 28 aspreviously described. In certain embodiments, the vias 38 a, 38 b extendless than an entire distance between the first face 30 and the secondface 32 of the first submount 18. In other embodiments, the vias 38 a,38 b may extend completely through the first submount 18. Notably, thesecond submount 68 provides mechanical and electrical isolation betweenthe vias 38 a, 38 b and the die attach pads 26, 28. In this regard, thedie attach pads 26, 28 and the LED chip 12 are buffered from anyexpanding or protruding of the vias 38 a, 38 b that may occur.Additionally, the vias 38 a, 38 b are still configured to dissipate heatfrom the LED chip 12 to the thermal pad 61. In FIG. 8, the electricallyconductive paths 63 a, 63 b may be arranged through both of the firstsubmount 18 and the second submount 68 between the die attach pads 26,28 and the package bond pads 34, 36.

FIG. 9 is a cross-sectional view of an LED package 70 that includesfirst and second die attach pads 26, 28 having thicknesses configured toprevent protruding vias from extending completely through the die attachpads 26, 28 according to embodiments disclosed herein. The LED package70 includes the LED chip 12 with the contact pads 22, 24 mounted on thesubmount 18 with the die attach pads 26, 28 and the package bond pads34, 36 as previously described. The encapsulant (20 of FIG. 2A) may alsobe provided on the LED chip 12 and the submount 18 as previouslydescribed. The first plurality of vias 38 a are registered with thefirst die attach pad 26 and the second plurality of vias 38 b areregistered with the second die attach pad 28 as previously described. InFIG. 9, the die attach pads 26, 28 comprise increased thicknesses suchthat any expanding or protruding of the vias 38 a, 38 b may extend lessthan an entire distance through either of the die attach pads 26, 28. Inthis manner, good thermal and electrical contact between the contactpads 22, 24 and the die attach pads 26, 28 is maintained. In certainembodiments, the first die attach pad 26 and the second die attach pad28 comprise a thickness that is at least twice as high as previouslydescribed. For example, in certain embodiments, the thickness of the dieattach pads 26, 28 can be up to about 200 μm, or in a range of about 10μm to about 180 μm, or in a range of about 80 μm to about 160 μm. Incertain embodiments, the submount 18 comprises one or more additionalvias 38 c that are arranged outside of a mounting area defined bylateral boundaries of the LED chip 12. In this regard, additionalthermally conductive paths are provided so heat that may dissipatelaterally in the die attach pads 26, 28 can in turn dissipate throughthe submount 18 outside of the mounting area of the LED chip 12.

According to certain embodiments disclosed herein, an LED package mayinclude a submount with vias configured in arrangements that provideimproved thermal dissipation for LED chips. In certain embodiments, atleast some of the vias may be arranged in close proximity to one anotherin a manner that certain vias overlap with one another to form a trenchvia in the submount. In this manner, a trench via provides a larger areafor heat that may be dissipated in localized areas of the submount. Incertain embodiments, a submount may include combinations of individualvias and trench vias. For example, one or more trench vias may bearranged in a submount underneath a mounting area for an LED chip andother individual vias may be arranged in other areas of the submount.Accordingly, positions of vias and trench vias may be tailored withinsubmounts to accommodate different heat profiles generated by differentLED packages.

FIG. 10A is a top view of a portion of the first face 30 of a submount74 that includes one or more trench vias 76 according to embodimentsdisclosed herein. The trench vias 76 may be formed by arranging multiplevias in close proximity to one another in a manner that certain viasoverlap with one another to form the one or more trench vias 76 in thesubmount. By way of example, the trench vias 76 illustrated in FIG. 10Aare formed by arranging five vias in close proximity to one another suchthat diameters or widths of the five vias overlap, thereby forming eachtrench via 76 that is continuous in the submount 74. As illustrated,each trench via 76 may comprise multiple curved edges corresponding tothe five vias that overlap. While the trench vias 76 are illustrated aslinear in FIG. 10A, in certain embodiments trench vias 76 may compriseone or more arcs or bends to form various nonlinear shapes in thesubmount 74. Trench vias 76 with nonlinear shapes may be formed byarranging multiple vias in close proximity to one another in nonlinearconfigurations. In certain embodiments, the trench vias 76 may be formedby other techniques, including continuously cutting or drilling adesired shape, e.g. linear or nonlinear, in the submount 74. In thismanner, the trench vias 76 may be configured with edges that aredifferent than the edges formed by overlapping vias as illustrated inFIG. 10A. For example, trench vias 76 may include elongated ovals,elongated rectangles, linear shapes, and nonlinear shapes with linear ornonlinear edges. The trench vias 76 provide localized areas withincreased thermally conductive material for heat dissipation. In FIG.10A, one of the trench vias 76 is registered with the first die attachpad 26, and another one of trench vias 76 is registered with the seconddie attach pad 28 of the submount 74. FIG. 10B is a bottom view of themounting face 16 of an LED chip 78 that is configured to be mounted onthe submount 74 of FIG. 10A. In certain embodiments, the first contactpad 22 and the second contact pad 24 of the LED chip 78 comprisecorresponding trench openings 80. The trench openings 80 may be formedby overlapping openings or by a single continuous opening. When the LEDchip 78 is mounted on the submount 74 of FIG. 10A, the trench openings80 are configured to be registered with the trench vias 76 of FIG. 10A.

According to certain embodiments disclosed herein, LED packages withmultiple LED chips may include one or more features configured toprovide improved thermal and/or electrical coupling between the multipleLED chips and submounts. In certain embodiments, it is desirable formultiple LED chips to be mounted on a submount in close proximity to oneanother. In this manner, when the multiple LED chips are electricallyactivated, the multiple LED chips may appear as a larger emitting areafor an LED package that is configured to operate at high output powerswith increase power densities. The multiple LED chips may be configuredto all generate the same color, or one or more of the LED chips may beconfigured to generate different colors. For LED packages with LEDsconfigured to generate different colors, having the multiple LEDs inclose proximity to one another may additionally provide improved colormixing or provide an emitting area or a pixel that is capable ofemitting different colors. When multiple LED chips are arranged in closeproximity to one another, heat tends to cluster in areas of the submountthat are central to the LED chips, thereby limiting operating powers andefficiencies of the LED chips. In certain embodiments, at least onethermally conductive element may be arranged between the multiple LEDchips on a submount. The thermally conductive element may be positionedcentrally to the multiple LED chips in areas where heat generation isthe highest. In certain embodiments, the submount may further comprise athermally conductive via that is registered with the thermallyconductive element. In this manner, heat that tends to cluster betweenmultiple LED chips may have a thermally conductive path away from themultiple LED chips.

FIG. 11A is a top view of at least a portion of an LED package 82 thatincludes a thermally conductive element 84 arranged between a pluralityof LED chips 86-1 to 86-4 on a face of a submount 88 according toembodiments disclosed herein. As illustrated, the plurality of LED chips86-1 to 86-4 are arranged on the first face 30 of the submount 88 inclose proximity to one another. The LED chips 86-1 to 86-4 may all beconfigured to generate the same color of light, such as a white, or theLED chips 86-1 to 86-4 may be separately configured to generatedifferent colors of light, such as different combinations of white, red,blue, and green light. The thermally conductive element 84 is arrangedon the first face 30 and centrally positioned with regard to the LEDchips 86-1 to 86-4. In certain embodiments, each LED chip of the LEDchips 86-1 to 86-4 is arranged adjacent to a different lateral edge ofthe thermally conductive element 84. In this manner, heat generated byeach of the LED chips 86-1 to 86-4 may conduct into the thermallyconductive element 84. As illustrated in FIG. 11A, in order for all ofthe LED chips 86-1 to 86-4 to be arranged adjacent a different lateraledge of the thermally conductive element 84, the LED chips 86-1 to 86-4are arranged in a pinwheel configuration where a corner of each of theLED chip 86-1 to 86-4 is arranged closest to a different corner of thethermally conductive element 84. In certain embodiments, the submount 88comprises a via 90 that is thermally conductive and registered with thethermally conductive element 84. In FIG. 11A, the via 90 is illustratedwith dashed lines to indicate it may not be visible in the top view. Incertain embodiments, the via 90 is configured with a samecross-sectional width or diameter as the thermally conductive element84. In other embodiments, the via 90 may be configured with across-sectional width or diameter that is larger or smaller than thethermally conductive element 84. In FIG. 11A, the dashed lines indicatethe via 90 has a larger cross-sectional width or diameter and mayaccordingly provide increased heat dissipation for the LED chips 86-1 to86-4. In certain embodiments, the configuration of the LED chips 86-1 to86-4, the thermally conductive element 84, and the via 90 illustrated inFIG. 11A may be replicated and repeated across a larger area of thesubmount 88 to form an LED array.

FIG. 11B is a cross-sectional view of the LED package 82 taken along thesection line labeled 11B in FIG. 11A. The LED chips 86-1 and 86-3 arevisible in this cross-sectional view and are arranged adjacent todifferent lateral edges of the thermally conductive element 84. Asillustrated, the via 90 extends between the first face 30 and the secondface 32 of the submount 88. A package bond pad 92 is configured on thesecond face 32 of the submount 88 and registered with the via 90. Inthis manner, a thermally conductive path is provided from the LED chips86-1, 86-3, through the thermally conductive element 84 and the via 90,and to the package bond pad 92. As previously described and indicated bythe dashed lines in FIG. 11B, the via 90 may comprise a cross-sectionalwidth or diameter that is the larger than a cross-sectional width ordiameter of the thermally conductive element 84.

FIGS. 11C, 11D, and 11E are top views of LED packages 82 similar to theLED package 82 of FIG. 11A, but with different arrangements of LED chipson the submount 88. In FIG. 11C, the plurality of LED chips 86-1 to 86-4are arranged such that a corner of each of the LED chips 86-1 to 86-4 isarranged closest to a different corner of the thermally conductiveelement 84. Rather than the pinwheel arrangement illustrated in FIG.11A, the LED chips 86-1 to 86-4 are arranged outwardly from thethermally conductive element 84 and away from lateral edges of thethermally conductive element 84. In this configuration, the LED chips86-1 to 86-4 are spaced further from one another around the thermallyconductive element 84. In this manner, heat from each LED chip 86-1 to86-4 has a further distance to travel to reach a different one of theLED chips 86-1 to 86-4. Heat may still tend to concentrate in positionscentral to the LED chips 86-1 to 86-4 and, accordingly, the thermallyconductive element 84 and the via 90 are configured to provide athermally conductive path away from the LED chips 86-1 to 86-4 andthrough the submount 88. In FIG. 11D, three LED chips 86-1 to 86-3 arearranged along or adjacent to three different lateral edges of thethermally conductive element 84. In FIG. 11E, two LED chips 86-1, 86-2are arranged along or adjacent to two different lateral edges of thethermally conductive element 84. In certain embodiments, the two LEDchips 86-1, 86-2 are arranged along or adjacent to two opposing lateraledges of the thermally conductive element 84. In FIG. 11D and FIG. 11E,the thermally conductive element 84 and the via 90 are configured toprovide thermally conductive paths as previously described.

According to certain embodiments disclosed herein, LED packages areconfigured to provide improved thermal and/or electrical couplingbetween LED chips and lead frames. In certain embodiments, an LED chipis arranged in a flip-chip configuration on a subassembly that is thenmounted to a lead frame in an LED package. The subassembly may compriseone or more die attach pads for the LED chip, one or more dielectriclayers, and one or more thermally conductive layers. The subassembly mayprovide a planar surface for mounting with the lead frame, therebyproviding improved thermal coupling between the LED chip and the leadframe. In certain embodiments, an underfill material may be arrangedbetween the lead frame and the LED chip or the subassembly to provideimproved mechanical support between the LED chip and the lead frame.

FIG. 12 is a cross-sectional view of an LED package 94 that includes alead frame 96 a, 96 b according to embodiments disclosed herein. The LEDpackage 94 includes the LED chip 12 with contact pads 22, 24 aspreviously described. The LED chip 12 is mounted over the lead frame 96a, 96 b. A first lead frame portion 96 a may comprise an anode or acathode for the LED package 94, and a second lead frame portion 96 b maycomprise the other of an anode or a cathode of the LED package 94. Thefirst lead frame portion 96 a is electrically isolated from the secondlead frame portion 96 b. The lead frame 96 a, 96 b is a structuretypically formed of metal, such as copper, copper alloys, or otherconductive metals. The lead frame 96 a, 96 b may initially be part of alarger metal structure that is singulated during manufacturing of LEDpackages. In certain embodiments of the LED package 94, an insulatingmaterial 98 is formed to surround portions of the lead frame 96 a, 96 b.In certain embodiments, the insulating material 98 is formed on the leadframe 96 a, 96 b before singulation so that the individual lead frameportions 96 a, 96 b may be electrically isolated from one another andmechanically supported in the LED package 94. The insulating material 98may form reflective sidewalls of a cup or a recess in the LED package 94where the LED chip 12 is mounted to the lead frame 96 a, 96 b. The leadframe portions 96 a, 96 b, which may respectively form the anode andcathode for the LED package 94, may be configured to protrude or beaccessible outside of the insulating material 98 to provide externalelectrical connections for the LED package 94. An encapsulant material100, such as silicone or epoxy, may fill the cup or recess toencapsulate the LED chip 12. In certain embodiments, a subassembly 102is arranged between the LED chip 12 and the lead frame 96 a, 96 b. Thesubassembly 102 may comprise first and second die attach pads 104, 106that are configured to be electrically coupled to different ones of thecontact pads 22, 24 of the LED chip 12. In this manner, the LED chip 12may be arranged in a flip-chip configuration on the first die attach pad104 and the second die attach pad 106. The subassembly 102 may furthercomprise a submount 108 that is mounted to at least one lead frameportion 96 b. In certain embodiments, the submount 108 comprises athermally conductive material that is configured to provide a thermallyconductive path from the LED chip 12 to the at least one lead frameportion 96 b. In certain embodiments, the submount 108 comprises a metalwith a thermal conductivity that is higher than other submountmaterials, such as aluminum oxide, alumina, AlN, PCBs, sapphire, Si, orSiC. One or more dielectric layers 110 may be provided between the dieattach pads 104, 106 and the submount 108 to provide electricalinsulation. The subassembly 102 may further provide a uniform mountingsurface that may be mounted to at least one of the lead frame portions96 a, 96 b (96 b in FIG. 12). Without the subassembly 102, the LED chip12 may be flip-chip mounted directly to the lead frame 96 a, 96 b suchthat the first contact pad 22 is electrically and mechanically coupledto the first lead frame portion 96 a, and the second contact pad 24 iselectrically and mechanically coupled to the second lead frame portion96 b. Due to manufacturing variances common to lead frames, the firstlead frame portion 96 a may not be completely planar with the secondlead frame portion 96 b. In this manner, if the LED chip 12 is directlyflip-chip mounted, uneven surfaces of the lead frame portions 96 a, 96 bmay prevent the LED chip 12 from making sufficient electrical andthermal contact. In order to provide electrical connections with the LEDchip 12, different wire bonds 112 may electrically couple the first leadframe portion 96 a to the first die attach pad 104 and the second leadframe portion 96 b to the second die attach pad 106.

FIG. 13 is a cross-sectional view of an LED package 114 that includes anunderfill material 116 configured to provide additional mechanicalsupport between the LED chip 12 and the lead frame 96 a, 96 b. Asillustrated, the LED chip 12 is flip-chip mounted to the lead frame 96a, 96 b such that the first contact pad 22 is electrically andmechanically coupled to the first lead frame portion 96 a, and thesecond contact pad 24 is electrically and mechanically coupled to thesecond lead frame portion 96 b. The underfill material 116 is arrangedbetween the LED chip 12 and the lead frame 96 a, 96 b to provideadditional mechanical support for the LED chip 12 to reduce thelikelihood the LED chip 12 becomes separated from the lead frame 96 a,96 b during operation. In certain embodiments, the underfill material116 is arranged between the first lead frame portion 96 a and the secondlead frame portion 96 b. The underfill material 116 may also be arrangedbetween the first contact pad 22 and the second contact pad 24 of theLED chip 12 and between lateral edges of the LED chip 12 and the leadframe 96 a, 96 b. After forming the underfill material 116, theencapsulant material 100 as previously described may be arranged betweensidewalls formed by the insulating material 98. In certain embodiments,the underfill material 116 comprises a material with a high durometervalue on a Shore hardness scale (e.g., a high durometer siliconematerial). A material with a high durometer value, or hardness, in theunderfill material 116 provides mechanical stability or anchoring forthe LED chip 12. For example, the underfill material 116 may comprise amaterial, such as silicone, with a Shore D hardness scale durometervalue of at least 40. In further embodiments, the underfill material 116may comprise a material with a Shore D hardness scale durometer value ina range of from about 40 to about 100 or in a range from about 60 toabout 80. In certain embodiments, the underfill material 116 includes asilicone material with a hardness that is higher than a siliconematerial of the encapsulant material 100. In other embodiments, theunderfill material 116 comprises epoxy. In still further embodiments,the underfill material 116 comprises light altering particles, such astitanium dioxide (TiO₂) particles suspended in a silicone binder. Inthis manner, light generated by the LED chip 12 that travels indirections toward the lead frame 96 a, 96 b may be redirected out of theLED package 114.

Those skilled in the art will recognize improvements and modificationsto the preferred embodiments of the present disclosure. All suchimprovements and modifications are considered within the scope of theconcepts disclosed herein and the claims that follow.

1. A light emitting diode (LED) package comprising: an LED chip mountedto a lead frame; a underfill material arranged between the LED chip andthe lead frame; and an encapsulant material arranged on the LED chip andthe underfill material.
 2. The LED package of claim 1, wherein a firstcontact of the LED chip is electrically and mechanically coupled with afirst lead frame portion, and a second contact of the LED chip iselectrically and mechanically coupled with a second lead frame portion.3. The LED package of claim 2, wherein the underfill material isarranged between the first lead frame portion and the second lead frameportion.
 4. The LED package of claim 2, wherein the underfill materialis arranged between the first contact of the LED chip and the secondcontact of the LED chip.
 5. The LED package of claim 1, wherein theunderfill material is arranged between lateral edges of the LED chip andthe lead frame.
 6. The LED package of claim 1, wherein the underfillmaterial comprises light-altering particles.
 7. The LED package of claim6, wherein the light-altering particles comprise titanium dioxide (TiO₂)particles that are suspended in a binder.
 8. The LED package of claim 7,wherein the binder comprises silicone.
 9. The LED package of claim 1,wherein the underfill material comprises epoxy.
 10. The LED package ofclaim 1, wherein the underfill material comprises a material with ahigher durometer value on a Shore D hardness scale than the encapsulantmaterial.
 11. The LED package of claim 1, wherein the underfill materialcomprises a material with a durometer value on a Shore D hardness scaleof at least
 40. 12. The LED package of claim 11, wherein the durometervalue is in a range from 40 to
 100. 13. The LED package of claim 1,further comprising an insulating material on the lead frame, wherein theinsulating material forms sidewalls of a cup in which the LED chip isarranged, and wherein the underfill material is arranged between thesidewalls of the cup.
 14. A light emitting diode (LED) packagecomprising: an LED chip mounted to a lead frame; and a subassemblyarranged between the LED chip and the lead frame, wherein thesubassembly comprises a metal submount that is thermally coupled betweenthe LED chip and the lead frame.
 15. The LED package of claim 14,wherein the subassembly further comprises: a first die attach pad thatis configured to be electrically coupled with a first contact pad of theLED chip; and a second die attach pad that is configured to beelectrically coupled with a second contact pad of the LED chip.
 16. TheLED package of claim 15, wherein the first die attach pad and the seconddie attach pad are electrically coupled to different portions of thelead frame by wirebonds.
 17. The LED package of claim 15, wherein thesubassembly further comprises a dielectric layer arranged between thefirst die attach pad and the metal submount and arranged between thesecond die attach pad and the metal submount.
 18. The LED package ofclaim 15, wherein the LED chip is arranged in a flip-chip configurationon the first die attach pad and the second die attach pad.
 19. The LEDpackage of claim 14, further comprising an underfill material arrangedbetween the subassembly and the lead frame.
 20. The LED package of claim14, further comprising an insulating material on the lead frame, whereinthe insulating material forms sidewalls of a cup in which the LED chipand the subassembly are arranged. 21-39. (canceled)